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cy7c1021bn/cy7c10211bn 1-mbit (64 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-06494 rev. *e revised september 16, 2013 1-mbit (64 k 16) static ram features temperature ranges ? commercial: 0 c to 70 c ? industrial: ?40 c to 85 c ? automotive-a: ?40 c to 85 c ? automotive-e: ?40 c to 125 c high speed ? t aa = 15 ns (automotive) complementary metal oxide semiconductor (cmos) for optimum speed/power low active power ? 825 mw (maximum) automatic power down when deselected independent control of upper and lower bits available in pb-free and non pb-free 44-pin tsop ii and 44-pin 400-mil-wide soj functional description the cy7c1021bn/cy7c10211bn is a high performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power down fe ature that sign ificantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from the input/output (i/o) pins (i/o 1 through i/o 8 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 9 through i/o 16 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking ce and output enable (oe ) low while forcing we high. if ble is low, then data from the memory location specified by the address pins appears on i/o 1 to i/o 8 . if bhe is low, then data from memory appears on i/o 9 to i/o 16 . see the truth table on page 11 for a complete description of read and write modes. the i/o pins (i/o 1 through i/o 16 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, we low). the cy7c1021bn/cy7c10211bn is available in standard 44-pin tsop type ii and 44-pin 400-mil-wide soj packages. use part number cy7c1021bn when ordering 15 ns t aa . 64k x 16 ram array i/o 1 ?i/o 8 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 512 x 2048 sense amps data in drivers oe a 2 a 1 i/o 9 ?i/o 16 ce we ble bhe a 8 logic block diagram
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 2 of 16 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 pin definitions .................................................................. 4 maximum ratings ............................................................. 5 operating range ............................................................... 5 electrical characteristics ................................................. 5 capacitance ...................................................................... 6 thermal resistance .......................................................... 6 ac test loads and waveforms ....................................... 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ......................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc? solutions ...................................................... 16 cypress developer community ................................. 16 technical support ................. .................................... 16
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 3 of 16 selection guide description cy7c1021b-15 maximum access time (ns) 15 maximum operating current (ma) commercial/industrial 130 automotive-a 130 automotive-e 130 maximum cmos standby current (ma) commercial/industrial 10 commercial/industrial (l version) 0.5 automotive-a (l version) 0.5 automotive-e 15 pin configuration figure 1. 44-pin soj/tsop ii pinout (top view) we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc a 4 a 3 oe v ss a 5 i/o 16 a 2 ce i/o 3 i/o 1 i/o 2 bhe nc a 1 a 0 18 17 20 19 i/o 4 27 28 25 26 22 21 23 24 nc v ss i/o 7 i/o 5 i/o 6 i/o 8 a 6 a 7 ble v cc i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 a 8 a 9 a 10 a 11
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 4 of 16 pin definitions pin name pin number i/o type description a 0 ?a 15 1?5,18?21, 24?27, 42?44 input address inputs used to select one of the address locations. i/o 1 ?i/o 16 7?10, 13?16, 29?32, 35?38 input/output bidirectional data i/o lines. used as input or output lines depending on operation. nc 22, 23, 28 no connect not connected to the die. we 17 input/control write enable input, active low. when selected low, a write is conducted. when deselected high, a r ead is conducted. ce 6 input/control chip enable input, active low. when low, selects the chip. when high, deselects the chip. bhe , ble 40, 39 input/control byte enable select inputs, active low. bhe controls i/o 16 ?i/o 9 , ble controls i/o 8 ?i/o 1 . oe 41 input/control output enable, active low. controls the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tristated, and act as input data pins. v ss 12, 34 ground ground for the device. should be connected to ground of the system. v cc 11, 33 power supply power supply inputs to the device.
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 5 of 16 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .......................................... ?55 ?? c to +125 ? c supply voltage on v cc relative to gnd [1] .................................?0.5 v to +7.0 v dc voltage applied to outputs in high z state [1] ................................. ?0.5 v to v cc + 0.5 v dc input voltage [1] .............................. ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature (t a ) [2] v cc commercial 0 ? c to +70 ? c 5 v ? 10% industrial ?40 ? c to +85 ? c automotive-a ?40 ? c to +85 ? c automotive-e ?40 ? c to +125 ? c electrical characteristics over the operating range parameter description test conditions -15 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.2 6.0 v v il input low voltage [1] ?0.5 0.8 v i ix input leakage current gnd < v i < v cc commercial / industrial ?1 +1 ? a automotive-a ?1 +1 ? a automotive-e ?4 +4 ? a i oz output leakage current gnd < v i < v cc , output disabled commercial / industrial ?1 +1 ? a automotive-a ?1 +1 ? a automotive-e ?4 +4 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc commercial / industrial ? 130 ma automotive-a ? 130 automotive-e ? 130 i sb1 automatic ce power down current ? ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max commercial / industrial ? 40 ma automotive-a ? 40 automotive-e ? 50 i sb2 automatic ce power down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 commercial / industrial ? 10 ma commercial / industrial (l) ? 0.5 automotive-a (l) ? 0.5 automotive-e ? 15 notes 1. v il (min.) = ?2.0 v and v ih (max) = v cc + 0.5 v for pulse durations of less than 20 ns. 2. t a is the ?instant on? case temperature.
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 6 of 16 capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 8 pf c out output capacitance 8pf thermal resistance parameter [3] description test conditions 44-pin soj 44-pin tsop ii unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 64.32 76.89 ? c/w ? jc thermal resistance (junction to case) 31.03 14.28 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms 90% 10% 3.0 v gnd 90% 10% all input pulses 5 v output 30 pf including jig and scope 5 v output 5 pf including jig and scope (a) (b) output r 481 ? r 481 ? r2 255 r2 255 ? 167 equivalent to: thvenin equivalent 1.73 v 30 pf rise time: 1 v/ns fall time: 1 v/ns 90% 10% gnd 90% 10% all input pulses output 30 pf including jig and scope output 5 pf including jig and scope (a) (b) output r2 ? r2 167 ? equivalent to: thvenin equivalent 30 pf rise time: 1 v/ns note 3. tested initially and after any design or proces s changes that may affect these parameters.
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 7 of 16 switching characteristics over the operating range parameter [4] description cy7c1021b-15 unit min max read cycle t rc read cycle time 15 ? ns t aa address to data valid ? 15 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 15 ns t doe oe low to data valid ? 7 ns t lzoe oe low to low z [4] 0 ? ns t hzoe oe high to high z [5, 6] ? 7 ns t lzce ce low to low z [5] 3 ? ns t hzce ce high to high z [5, 6] ? 7 ns t pu ce low to power up 0 ? ns t pd ce high to power down ? 15 ns t dbe byte enable to data valid ? 7 ns t lzbe byte enable to low z [5] 0 ? ns t hzbe byte disable to high z [5, 6] ? 7 ns write cycle [7] t wc write cycle time 15 ? ns t sce ce low to write end 10 ? ns t aw address setup to write end 10 ? ns t ha address hold from write end 0? ns t sa address setup to write start 0? ns t sd data setup to write end 8? ns t hd data hold from write end 0? ns t lzwe we high to low z [5] 3? ns t hzwe we low to high z [5, 6] ? 7 ns t bw byte enable to write end 9 ? ns notes 4. test conditions assume signal transition time of 3 ns or less, timing reference leve ls of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30 pf load capacitance. 5. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , t hzbe is less than t lzbe , and t hzwe is less than t lzwe for any device. 6. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured ? 500 mv from steady-state voltage. 7. the internal write time of the memory is defined by the overlap of ce low, we low, and bhe / ble low. ce , we, and bhe / ble must be low to initiate a write, and the transition of these signals can terminate the write. the input data setup and hold timing should be referenced to the l eading edge of the signal that terminates the write.
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 8 of 16 switching waveforms figure 3. read cycle no. 1 [8, 9] figure 4. read cycle no. 2 (oe controlled) [9, 10] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high icc isb impedance data t dbe t lzbe t hzce i cc i sb address oe ce bhe ,ble out v cc supply current notes 8. device is continuously selected. oe , ce , bhe , and bhe = v il . 9. we is high for read cycle. 10. address valid prior to or coincident with ce transition low.
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 9 of 16 figure 5. write cycle no. 1 (ce controlled) [11, 12] figure 6. write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw data address bhe , t ce address we ble i/o t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce notes 11. data i/o is high impedance if oe or bhe and/or ble = v ih . 12. if ce goes high simultaneously with we going high, the output remains in a high impedance state.
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 10 of 16 figure 7. write cycle no. 3 (we controlled, oe low) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 11 of 16 truth table ce oe we ble bhe i/o 1 ?i/o 8 i/o 9 ?i/o 16 mode power hxxxx high z high zpower down st andby (i sb ) l l h l l data out data out read - all bits active (i cc ) l h data out high z read - lower bits only active (i cc ) h l high z data out read - upper bits only active (i cc ) l x l l l data in data in write - all bits active (i cc ) l h data in high z write - lower bits only active (i cc ) h l high z data in write - upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc )
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 12 of 16 ordering information cypress offers other versions of this product type in many di fferent configurations and features. the following table contains only the list of parts that are currently available. for a complete listing of all options, refer to the product summary page at http://www.cypre ss.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution center s, manufacturers? representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices. ordering code definitions speed (ns) ordering code package diagram package type operating range 15 cy7c1021bnl-15vxc 51-85082 44-pin (400-mil) molded soj (pb-free) commercial cy7c1021bn-15vxe automotive-e cy7c1021bnl-15zxi 51-85087 44-pin tsop type ii (pb-free) industrial cy7c1021bnl-15zsxa 51-85087 44-pin tsop type ii (pb-free) automotive-a cy7c1021bn-15zsxe automotive-e temperature range: x = c or i or a or e c = commercial; i = industrial; a = automotive-a; e = automotive-e pb-free package type: xx = v or z or zs v = 44-pin (400-mil) molded soj z or zs = 44-pin tsop type ii speed: 15 ns low power bn = 250 nm technology x = blank or 1 blank = 12 ns or 15 ns; 1 = 10 ns bus width: 16 bits 02 = 2-mbit density 1 = fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c cy 1 - 15 xx 7 02 x bn 1 x x l
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 13 of 16 package diagrams figure 8. 44-pin soj (400 mils) v44.4 package outline, 51-85082 figure 9. 44-pin tsop z44- ii package outline, 51-85087 51-85082 *e 51-85087 *e
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 14 of 16 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable soj small outline j-lead sram static random access memory tsop thin small outline package ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ma milliampere mm millimeter mw milliwatt ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy7c1021bn/cy7c10211bn document number: 001-06494 rev. *e page 15 of 16 document history page document title: cy7c1021bn/cy7c10211 bn, 1-mbit (64 k 16) static ram document number: 001-06494 rev. ecn no. submission date orig. of change description of change ** 423877 see ecn nxr new data sheet. *a 505726 see ecn nxr removed i os parameter from dc electrical characteristics table. added automotive products updated ordering information table *b 2897061 03/22/10 aju removed obsolete pa rts from ordering information table updated package diagrams *c 2947254 06/08/10 rame corrected ?byte wr ite select inputs? to ?byte enable select inputs? on page 2. added ohm ( ? )symbol inthevenin equivalent circuit on page 4. included t hzbe and t lzbe to switching characteristics table footnote 2 included operating range for cy7c1021bnl -15zxi in ordering information ta- ble. *d 3328634 26/07/2011 aju updated features (removed the information associated with speed bins -10 and -12). removed the note ?for best practice recommendations, refer to the cypress application note, sram system design guidelines-an1064.? in page 1 and its reference in functional description . updated functional description (removed the information associated with speed bins -10 and -12). updated selection guide (removed the information associated with speed bins -10 and -12). updated electrical characteristics (removed the information associated with speed bins -10 and -12). updated switching characteristics (removed the information associated with speed bins -10 and -12). updated ordering information . added acronyms and units of measure . updated in new template. *e 4125119 09/16/2013 vini updated package diagrams : spec 51-85082 ? changed revision from *c to *e. spec 51-85087 ? changed revision from *c to *e. updated in new template. completing sunset review.
document number: 001-06494 rev. *e revised september 16, 2013 page 16 of 16 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1021bn/cy7c10211bn ? cypress semiconductor corporation, 2006-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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